Bernin (France), June 3, 2025 – Soitec (Euronext – Tech Leaders), a world leader in the design and production of innovative semiconductor materials, today announced a strategic collaboration with ...

By using advanced "3D stacking" technology, Izmo re-engineered a standard 200mm x 200mm electronics board into a compact 81mm ...

TL;DR: Huawei is set to lead Apple by integrating high-performance HBM DRAM with 3D stacking technology in smartphones, boosting AI efficiency and bandwidth while reducing chip size. Apple plans to ...

The semiconductor companies and startups on the front lines of the AI chip market are competing over scale as much as anything else. They’re all racing to roll out giant graphics processing units ...

Intel has a new 3D technology to allow for 3D chip stacking, despite previous problems with this type of capability. Share on Facebook (opens in a new window) Share on X (opens in a new window) Share ...

Intel's next-gen Xeon "Clearwater Forest" CPUs will feature up to 288 cores based on the new Darkmont CPU architecture, with no P-Cores in sight with Clearwater Forest, its 288 E-Cores. The latest ...

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization ...

Samsung Electronics has successfully stacked the next-gen 3D DRAM to 16 layers, twice as many as its competitor Micron. According to reports from TheElec and ZDNet Korea, citing industry sources, ...

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher ...

Designers, who need to build high performance real-time sensing systems, are greatly challenged since every building block in the system needs to be built with a technology that allows that building ...