Semiconductor Engineering

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)

A new technical paper titled “CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing” was published by researchers at University of California, Riverside. “Secure ...
Semiconductor Engineering

SVT (Six Stacked Vertical Transistors) SRAM Cell Architecture Introduction: Design And Process Challenges Assessment

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual ...
Design-Reuse

MoSys Announces Quad-Density Memory Technology; 1T-SRAM-Q Technology Enables New Levels of On-Chip Memory

SUNNYVALE, Calif. & TOKYO--(BUSINESS WIRE)--Dec. 16, 2002--MoSys, Inc. (Nasdaq:MOSY), the industry's leading provider of high density SoC embedded memory solutions, today introduced 1T-SRAM-Q(TM) ...
Design-Reuse

Dolphin Integration sRAM compiler completes TSMC IP9000 Level 1 qualification at 85 nm Ultra Low Power process

Grenoble, France – June 15, 2012. Dolphin Integration announces that the new memory architecture RHEA has now passed the Level 1 criteria of TSMC’s stringent IP9000 qualification program. “We ...