Semiconductor Engineering

Why Scan Diagnosis Should Be Part Of Every Fabless Company’s Yield Playbook

Provide practical KPIs to monitor, including FA hit rate (percent of FAs that find root cause) and time to address yield ...
EDN

DFT Analyzer Validates Design-For-Test Features

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...
Semiconductor Engineering

Packetized Scan Test Delivery

The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...
EDN

Design-for-test analyzer validates boundary-scan

Richardson, Texas—A product called DFT Analyzer from ASSET InterTech, Inc., a maker of IEEE-1149.1/JTAG boundary-scan test and ISP (in-system programming) tools, promises to reduce manufacturing and ...
Electronic Design

Expanded Role for JTAG DFT

In recent years, boundary scan has transformed itself. JTAG started more than a decade ago as a simple structural interconnect test technology. It now is a foundational embedded infrastructure capable ...
Electronic Design

Reducing the Cost of Test in 2003

This year, there are many more ways being developed to reduce the cost of test than there are ATE companies. In anticipation of the elusive economic upturn, recently introduced testers and updates to ...