Semiconductor Engineering

Conquer Placement And Clock Tree Challenges In HPC Designs

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Races, missed next-state values due to long paths, and metastability can result from corrupted clock signals. This post describes the challenges of clock network and clock jitter analysis in more ...
Electronic Design

Demand for Automotive Timing Requirements Puts Focus on Clock Generators

The number of precision reference clocks needed in automotive electronics is increasing complexity in system design and changing best practices. The benefits of changing timing requirements from ...